Renesas Electronics /R7FA6T2BD /ADC_B /ADTRGDLR1

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Interpret as ADTRGDLR1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TRGDLY20TRGDLY3

Description

A/D Conversion Start Trigger Delay Register 1

Fields

TRGDLY2

Scan Group 2 Trigger Input Delay Configuration

TRGDLY3

Scan Group 3 Trigger Input Delay Configuration

Links

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